The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device which has a trench gate type structure.
Semiconductor devices, such as power metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor), have been used for various kinds of fields including the field for electric power control. In these semiconductor devices, it is desired to increase the efficiency in order to meet the demand of saving of energy in recent years.
In order to satisfy the demand, it is effective to reduce the electrical conduction loss, i.e., “ON resistance” of the element. So far, reducing ON resistance has been sought by carrying out the miniaturization of the cell. Moreover, by adopting a “trench gate structure” as the element structure, the channel width has been made greater and the channel density has been increased sharply.
Currently, the further miniaturization of the trench gate structure is being carried out, and ON resistance of the element has come to be improved sharply. As an example which indicated the trench gate type semiconductor device where the channel density has been increased, Japanese Patent Laid-Open Publication No.2001-102579 can be mentioned which discloses a device where increase of the channel density and promotion of the degree modulation of conduction are compatible by adopting a ladder-like trench gate structure.
FIG. 23 is a schematic diagram showing the semiconductor device which was examined by the inventors of the present invention in the course of attaining this invention.
That is, this figure shows the cross-sectional structure near the gate of a trench gate type n channel type MOSFET. An n− type epitaxial region 6 and a p type base region 5 are formed on an n+ type substrate 7. Trenches are formed from the surface to the epitaxial layer 6, and are embedded with a gate oxide 3 and a gate electrode 1 to form an embedded gate structure. An insulating interlayer film 4 is provided appropriately on the embedded gate, and n type source regions 2 are formed around the trenches. Further, a drain region 8 is appropriately provided in the back side of the substrate 7.
By applying a predetermined bias voltage to the gate electrode 1, this MOSFET can form a channel region in the circumferences of the embedded trenches, and can carry out switching operation which changes the conduction state between the source region 2 and the drain regions 8 into “ON” state.
Now, in such a semiconductor device, in order to improve the efficiency of operation, it is important to reduce a “parasitic capacitance” as well as reducing the “ON resistance”, and to increase the operating speed.
For example, when performing inverter control, for example, combining two or more switching elements, if the operating speed of the elements is slow, it is necessary to set up a “dead time” which serves as “OFF” in all the switching elements that constitute an arm for a long time in order to prevent the penetration current of a rectification arm. As a result, a loss increases. On the other hand, if the operating speed becomes larger by reducing the parasitic capacitance of the switching elements, the “dead time” can be shortened and the loss can be reduced.
The parasitic capacitance of the semiconductor device illustrated in FIG. 23 can be divided into some constituents.
First, the capacitance (Cgd) between the drain and the gate can be mentioned. This capacitance is produced in the region where the epitaxial region 6 and gate oxide 3 are in contact with. Next, the capacitance (Cds) between the drain and the source can be mentioned. This capacitance is produced in the p-n junction where the epitaxial region 6 and the base region 5 touch.
Moreover, the capacitance (Cgs) between the gate and the source can be mentioned. This capacitance is produced in the regions where the gate oxide 3 and the source region 2 touch, and where the gate oxide 3 and the base region 5 touch.
Since these capacitance constituents do loss to switching operation of the semiconductor device, they need to be reduced. In order to reduce the capacitance, it may be considered to make area of these contact parts smaller, or to promote depletion by lowering the carrier concentration of each semiconductor region, etc.
However, if these methods are employed, there will be a problem that it becomes difficult to juggle the “ON resistance” and the “parasitic capacitance”, or to juggle the “breakdown voltage” and the “parasitic capacitance” of the semiconductor device. Thus, an improvement of a total performance becomes difficult.